Set ‘Project Location’ and leave the rest as default, then click ‘Ok.’ ‘Add items to the Project’ window pops up (Fig. 2), select a suitable name for your project. Create a project by clicking ‘JumpStart’ in the welcome screenģ. Start ModelSim from the desktop you will see ModelSim 10.4a dialogue windowĢ. To simulate the LFSR design, install ModelSim V10.4a on a Windows PC and follow the steps given below:ġ. In this project, the register transfers up to eight bits (length=8) using the code: The movement of data through the register under simulation is shown in binary and hexadecimal formats. Each bit of the register is assigned a value concurrently with the other bits the order of the listed non-blocking assignments is of no consequence. The sample Verilog code (lfsr_tb.v.) is written for an eight-cell autonomous LFSR with a synchronous (edge-sensitive) cyclic behaviour using RTL design. Here, the LFSR loops through repetitive sequences of pseudo-random values. Therefore it generates pseudo-random cycle sequence of binary values. The block diagram shown here has CN =1 because Y is connected directly to the input of the first stage.Īn LFSR is basically a sequential shift register with a combinational feedback logic. 1 has binary tap coefficients C1….CN that determine whether Y(N) is fed back to a given stage of the register. The response to these patterns can be compared to the circuit’s expected response and thereby reveal the presence of an internal fault. An autonomous LFSR can be a random pattern generator providing stimulus patterns to a circuit. The sample block diagram of a 4-bit LFSR is shown in Fig. Therefore hardware and software implementations of LFSRs are common. There are numerous applications where LFSRs are used as pseudo-random numbers, pseudo-noise sequences and fast digital counters. Thus an LFSR is most often a shift register whose input bit is driven by the XOR of some bits of the overall shift register. The most commonly used linear function of a single bit is Exclusive OR (XOR). It is a shift register whose input bit is a linear function of its previous state. Linear-feedback shift registers are commonly used in data-compression circuits implementing a signature analysis technique called cyclic-redundancy check (CRC).Īutonomous LFSRs are used in applications requiring pseudo-random binary numbers. 1: Sample block diagram of a 4-bit LFSR LFSR This project describes the RTL model of a synchronous circuit-an autonomous LFSR that executes concurrent transformations on a data path under the synchronising control of its input clock signal. Register-transfer level (RTL) models are quite popular in the industry as these can be easily synthesised using latest electronic design automation (EDA) tools. Presented here is a linear-feedback shift register (LFSR) using Verilog that is designed and simulated using ModelSim testbench.
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